Most of the research in the field of nanoelectronics has been focused on nanodevices and fabrication aspects and as a result a variety of nanodevice technologies have been demonstrated. By contrast, very little work has been reported on the design and evaluation of circuits and computational architectures using nanodevices. There is similarly not much work on the impact of device and fabric (e.g., the 2-D nanowire array) properties on computing. In this paper, we focus on computing architectures based on silicon nanowires.
With recent promising progress on nanoscale devices including semiconductor nanowires and nanowire crossbars, researchers are trying to explore the possibility of building nanoscale computing systems. We have designed a nanoscale application-specific architecture called NASIC, which is based on semiconductor nanowire grids and FETs at crosspoints. In this paper, we propose a built-in redundancy technique to tolerate the defects in our nanoscale architecture. Compared to other fault tolerance techniques, our solution has significant advantages including self-healing, higher density.
