Emerging nano-device based architectures are expected to experience high defect rates associated with the manufacturing process. In this paper, we introduce a novel built-in heterogeneous fault-tolerance scheme, which incorporates redundant circuitry into the design to provide fault tolerance. A thorough analysis of the new scheme was carried out for various system level metrics. The implementation and analysis were carried out on WISP-0, a stream processor implemented on the Nanoscale Application Specific Integrated Circuits (NASIC) fabric.
Emerging nano-device based architectures will be impacted by parameter variation in conjunction with high defect rates. Variations in key physical parameters are caused by manufacturing imprecision as well as fundamental atomic scale randomness. In this paper, the impact of parameter variation on Nanoscale Cognitive Computing Fabrics is extensively studied through a novel integrated methodology across device, circuit and architectural levels. This integrated framework enables to study in detail the impact of physical parameter variation across all fabric layers for the first time.
Various fault-tolerance techniques have been proposed in recent years to tolerate the high defect rates expected in emerging nanofabrics with unconventional nano-manufacturing techniques. The proposed techniques include modular redundancy schemes that use majority voters to vote on the ‘0’ or 1’ outputs of redundant modules. Novel nanoscale computational fabrics employ new circuit and logic styles where the likelihood of occurrence of faulty ‘1’s and faulty ‘0’s may not be identical. This provides an opportunity for using biased voting (towards logic ‘1’ or ‘0’) to achieve improved yield.
