A new 3D IC fabric named NP-Dynamic Skybridge is proposed that provides fine-grained vertical 3D integration for future technology scaling. Relying on a template of vertical nanowires, it expands our prior work to incorporate and utilize both n- and p-type transistors in a novel NP-Dynamic circuit-style compatible with true 3D integration. This enables a wide range of elementary logics leading to more compact circuits, simple clocking schemes for cascading logic stages and low buffer requirement. We detail new design concepts for larger-scale circuits, and evaluate our approach using a 4-bit nanoprocessor implemented in 16 nm technology node. A new pipelining scheme specifically designed for our 3D NP-Dynamic circuits is employed in the nanoprocessor. We compare our approach with 2D CMOS as well as state-of-the-art transistor-level monolithic 3D IC (T-MI) approach. Benchmarking results for the 4-bit nanoprocessor show benefits of up to 56.7x density, 3.8x power and 1.7x throughput over 2D CMOS. Compared with T-MI, our new 3D fabric showed 31x density, 3x power and 1.4x throughput improvement. Additional evaluation of 4-bit and 8-bit CLA designs shows that significantly improved gains can be achieved for our 3D approach over 2D CMOS with increasing circuit bit-width, indicating potential for future scalability.