In an earlier paper about the FlexCache project, we described our vision of a multipartitioned cache where memory accesses are separated based on their static predictability and memory footprint, and managed with various compiler controlled techniques supported by instruction set architecture extensions, or with traditional hardware control.
In line with that vision, this paper describes our work in progress related to the memory performance and memory management of scalars. Our focus in this paper is embedded multimedia architectures, but the methodology described can be applied to other classes of applications.
In particular, we establish the minimum size of a memory partition that would allow us to map and manage all scalar accesses in a program statically, and describe compiler techniques to automate the extraction of this information. Additionally, we study the cache behavior of scalar accesses for theses architectures, including reduction in cache misses due to separation of scalars from other types of memory accesses. Finally, we evaluate the impact of register file size on the volume of scalar related memory accesses, and its impact on the applications' overall cache performance.