Compact models are integral part of large-scale integrated circuit simulations and validation of new technologies. With technology scaling, however, compact models have become complex with lots of parameters involved. Hence, parameter extraction for new device technology is rather challenging. In this paper, we propose a probabilistic approach to compact model parameter extraction. We devise a Bayesian optimization technique which is specifically tailored for efficient extraction of BSIMCMG parameters for fitting nanowire junctionless transistors and 14nm FinFETs. The Bayesian optimization based extraction results show excellent fit to drain current data, with 6.5% normalized root-mean-square error for nanowire junctionless transistors. For a 14nm FinFET, the technique achieves 6.3% and 1.5% for drain current and capacitance data, respectively. This compares favourably to current tools available as well and improves on current tools available including industrial ones.