Process variation is expected to persist in the various novel nanoscale fabrics being proposed to replace CMOS. Logic circuits built using non-traditional and bottom-up techniques will need to meet new design rules, such as tolerance of high defect rates and use of regular structures in layout. One circuit fabric type that meets these requirements is grid-based logic, with builtin fault resilience provided by 2-way redundancy. In this work, we show that this fabric design also is able to tolerate substantial process variation in addition to its defect resistance.