Variation and Fault Tolerance at Nanoscale
Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization with Fault Tolerance
Structure Discovery for Gene Expression Networks with Emerging Stochastic Hardware
Skybridge: 3-D Integrated Circuit Technology Alternative to CMOS
Impact of Process Variation in Fault-Resilient Streaming Nanoprocessors
Self-Healing Wire-Streaming Processors on 2-D Semiconductor Nanowire Fabrics
Towards Defect-Tolerant Nanoscale Architectures
Combining Circuit Level and System Level Techniques for Defect-Tolerant Nanoscale Architectures
Fault-Tolerant Nanoscale Processors on Semiconductor Nanowire Grids
Combining 2-level Logic Families in Grid-based Nanoscale Fabrics
Pages
