Nano-crossbar arrays have emerged as area and power efficient structures with an aim of achieving high performance computing beyond the limits of current CMOS. Due to the stochastic nature of nano-fabrication, nano arrays show different properties both in structural and physical device levels compared to conventional

Non-volatile 3D FPGA research to date utilizes layer-by-layer stacking of 2D CMOS / RRAM circuits. On the other hand, vertically-composed 3D FPGA that integrates CMOS and RRAM circuits has eluded us, owing to the difficult requirement of highly customized regional doping and material insertion in 3D to build and route complementary p- and n-type transistors as well as resistive switches. In the layer-by-layer nonvolatile 3D FPGA, the connectivity between the monolithically stacked RRAMs and underlying CMOS circuits is likely to be limited and lead to large parasitic RCs.

Thermal management is one of the critical challenges in 3D integrated circuits. Incorporating thermal optimizations during the circuit design stages requires a convenient automatic method of doing thermal characterization for feedback purposes. In this paper, we present a methodology, which supports thermal characterization by automatically extracting the steady-state thermal modeling resistance network from a post-placement physical design. The method follows a two-level hierarchical approach.

This paper introduces a new fine-grained 3D IC fabric technology called NP-Dynamic Skybridge. Skybridge is a family of 3D IC technologies that provides fine-grained vertical integration. In comparison to the original 3D Skybridge, the NP-Dynamic approach enables a more comprehensive logic style for improved efficiency. It addresses device, circuit, connectivity and manufacturability requirements with an integrated 3D mindset. The NP-Dynamic 3D circuit style enables wide range of logic expressions, simple clocking scheme, and reduces buffer requirements.

Migration to 3-D provides a possible pathway for future Integrated Circuits (ICs) beyond 2-D CMOS, which is at the brink of its own fundamental limits. Partial attempts so far for 3-D integration using die to die and layer to layer stacking do not represent true progression , and suffer from their own challenges with lack of intrinsic thermal management being among the major ones. Our proposal for 3-D IC, Skybridge, is a truly fine-grained vertical nanowire based fabric that solves technology scaling challenges, and at the same time achieves orders of magnitude benefits over 2-D CMOS.