Nanoscale Application Specific Integrated Circuits

This chapter provides an overview of the Nanoscale Application Specific IC (NASIC) fabric. The NASIC fabric has spun several research directions by multiple groups. This overview is a snapshot of the thinking, techniques and some of the results as of to date. NASICs is targeted as a CMOS-replacement technology. The project encompasses aspects from the physical layer and manufacturing techniques, to devices, circuits and architectures, and is funded by NSF, and FENA/FCRP and CHM/NSEC nanotechnology centers.

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Integrated Nanowire Systems for Post-CMOS Computing

CMOS faces new device and technology challenges: MOSFETs require ultra-sharp doping profiles and complex processing; integration of devices into circuits requires arbitrary interconnection with overlay precision beyond known manufacturing solutions (3σ=±3nm, 16nm CMOS, ITRS’11[1]). To overcome these challenges, we propose a new nanoscale computing fabric with integrated design of device, interconnect and circuits to minimize manufacturing requirements while providing ultra-dense, high-performance, and low-power solution surpassing scaled CMOS.

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On-Chip Variation Sensor for Systematic Variation Estimation in Nanoscale Fabrics

Parameter variations caused by manufacturing imprecision at the nanoscale are expected to cause large deviations in electrical characteristics of emerging nanodevices and nano-fabrics leading to performance deterioration and yield loss. Parameter variation is typically addressed pre-fabrication, with circuit design targeting worst-case timing scenarios. By contrast, if variation is estimated post-manufacturing, adaptive techniques or reconfiguration could be used to provide more optimal level of tolerance.

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Heterogeneous Integration of Epitaxial Nanostructures: Strategies and Application Drivers

In order to sustain the historic progress in information processing, transmission, and storage, concurrent integration of heterogeneous functionality and materials with fine granularity is clearly imperative for the best connectivity, system performance, and density metrics. In this paper, we review recent developments in heterogeneous integration of epitaxial nanostructures for their applications toward our envisioned device-level heterogeneity using computing nanofabrics.

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N3ASICs: Designing Nanofabrics with Fine-Grained CMOS Integration

We propose a novel nanofabric approach that mixes unconventional nanomanufacturing with CMOS manufacturing flow and design rules in order to build a reliable nanowire-CMOS fabric called N3ASIC with no new manufacturing constraints added. Active devices are formed on a dense uniform semiconductor nanowire array and standard area distributed pins/vias; metal interconnects route the signals in 3D. CMOS design rules are followed. Novel nanowire based devices are envisioned and characterized based on 3D physics modeling.

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N3ASIC Based Nanowire Volatile RAM

As CMOS technology advances into the nanoscale, the continuous push for low power, high performance, and dense volatile memory is reaching its limit. Moreover, in the nanometer regime complex design rules and manufacturing costs are escalating as it is getting increasingly difficult to control manufacturing process parameters. In this paper, we propose a novel 10 transistor based volatile Nanowire Random Access Memory (10T-NWRAM) which is highly scalable and manufacturing friendly since it is based on the very regular N3ASIC fabric.

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FastTrack: Towards Nanoscale Fault Masking with High Performance

High defect rates are associated with novel nanodevice-based systems owing to unconventional and self-assembly based manufacturing processes. Furthermore, in emerging nanosystems, fault mechanisms and distributions may be very different from CMOS due to unique physical layer aspects, and emerging circuits and logic styles. Development of analytical fault models for nanosystems is necessary to explore the design of novel fault tolerance schemes that could be more effective than conventional schemes.

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Integrated Device-Fabric Explorations and Noise Mitigation in Nanoscale Fabrics

An integrated device-fabric methodology for evaluating and validating Nanoscale Cognitive Computing Fabrics is presented. The methodology integrates physical layer assumptions for materials and device structures with accurate 3-D simulations of device electrostatics and operations and circuit level noise and cascading validations. Electrical characteristics of six different Crossed Nanowire Field Effect Transistors (xnwFETs) are simulated and current and capacitance data obtained.

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Nanowires