Emerging nano-device based architectures will be impacted by parameter variation in conjunction with high defect rates. Variations in key physical parameters are caused by manufacturing imprecision as well as fundamental atomic scale randomness. In this paper, the impact of parameter variation on Nanoscale Cognitive Computing Fabrics is extensively studied through a novel integrated methodology across device, circuit and architectural levels. This integrated approach enables to study in detail the impact of physical parameter variation across all fabric layers.

SRAM based memory blocks constitute a major part of state-of-art processor architectures. Increasing complexity and variation in nanometer CMOS fabrication has prompted exploration of memory circuits based on emerging nanofabrics. In this work, we propose a new 8T-Nanowire based RAM (8T-NWRAM) circuit for high density memory arrays. The design is based on N3ASIC, a nanofabric using combination of crosspoint nanowire FETs and integration with metal interconnects. The layout implementation is optimized to reduce bitline load and achieve high performance.

Reliable and scalable manufacturing of nanofabrics entails significant challenges. Scalable nanomanufacturing approaches that employ the use of lithographic masks in conjunction with nanofabrication based on self-assembly have been proposed. A bottom-up fabrication of nanoelectronic

Several nanoscale-computing fabrics based on novel materials such as semiconductor nanowires, carbon nanotubes, graphene, etc. have been proposed in recent years. However, their integration and interfacing with external CMOS has received only limited attention. In this paper we explore integration challenges for nanoscale fabrics focusing on registration and overlay requirements especially. We address the following questions: (i) How can we mitigate the overlay requirements between nano-manufacturing and conventional lithography steps?

Various fault-tolerance techniques have been proposed in recent years to tolerate the high defect rates expected in emerging nanofabrics with unconventional nano-manufacturing techniques. The proposed techniques include modular redundancy schemes that use majority voters to vote on the ‘0’ or 1’ outputs of redundant modules. Novel nanoscale computational fabrics employ new circuit and logic styles where the likelihood of occurrence of faulty ‘1’s and faulty ‘0’s may not be identical. This provides an opportunity for using biased voting (towards logic ‘1’ or ‘0’) to achieve improved yield.