Nanoscale processor designs pose new challenges not encountered in the world of conventional CMOS designs and manufacturing. Nanoscale devices based on crossed semiconductor nanowires (NWs) have promising characteristics in addition to providing great density advantage over conventional CMOS devices. This density advantage could, however, be easily lost when assembled into nanoscale systems and especially after techniques dealing with high defect rates and manufacturing related layout/doping constraints are incorporated.

The rapid progress of manufacturing nanoscale devices is pushing researchers toexplore appropriate nanoscale computing architectures for high density beyond the physical limitations of conventional lithography. However, manufacturing and layout constraints, as well as high defect/fault rates expected in nanoscale fabrics, could make most device density lost whenintegrated into computing systems. Therefore, a nanoscale architecture that can deal with those constraints and tolerate defects/faults at expected rates, while still retaining the density advantage, is highly desirable.

A new processing architecture for semiconductor nanowire grid fabrics is presented. The system consists of a large number of functionally identical units called cells. Cells are locally interconnected with nearest neighbors, with a limited number of global signals routed from supporting CMOS circuitry. One possible implementation of a digital Cellular Neural Network (CNN) using this architecture is shown. The digital cellular design may be up to 27X denser than an equivalent 18nm CMOS implementation.

Most proposed nanoscale computing architectures are based on a certain type of two-level logic family, e.g.,AND–OR, NOR–NOR, NAND–NAND, etc. In this paper, a new fabric architecture that combines different logic families in the same nanofabric is proposed for higher density and better defect tolerance. To achieve this, we apply very minor modifications on the way of controlling nanogrids, while the basic manufacturing requirements remain the same. The fabric that is based on the new heterogeneous two-level logic yields higher density for the applications mapped to it.

Emerging nano-device based architectures are expected to experience high defect rates associated with the manufacturing process. In this paper, we introduce a novel built-in heterogeneous fault-tolerance scheme, which incorporates redundant circuitry into the design to provide fault tolerance. A thorough analysis of the new scheme was carried out for various system level metrics. The implementation and analysis were carried out on WISP-0, a stream processor implemented on the Nanoscale Application Specific Integrated Circuits (NASIC) fabric.