At Sub-20nm technologies CMOS scaling faces severe challenges primarily due to fundamental device scaling limitations, interconnection overhead and complex manufacturing. Migration to 3-D has been long sought as a possible pathway to continue scaling; however, CMOS’s intrinsic requirements are not compatible for fine-grained 3-D integration. In [1], we proposed a truly fine-grained 3-D integrated circuit fabric called Skybridge that solves nanoscale challenges and achieves orders of magnitude benefits over CMOS.

A new processing architecture for semiconductor nanowire grid fabrics is presented. The system consists of a large number of functionally identical units called cells. Cells are locally interconnected with nearest neighbors, with a limited number of global signals routed from supporting CMOS circuitry. One possible implementation of a digital Cellular Neural Network (CNN) using this architecture is shown. The digital cellular design may be up to 27X denser than an equivalent 18nm CMOS implementation.

Process variation is expected to persist in the various novel nanoscale fabrics being proposed to replace CMOS. Logic circuits built using non-traditional and bottom-up techniques will need to meet new design rules, such as tolerance of high defect rates and use of regular structures in layout. One circuit fabric type that meets these requirements is grid-based logic, with builtin fault resilience provided by 2-way redundancy. In this work, we show that this fabric design also is able to tolerate substantial process variation in addition to its defect resistance.

Junctionless field-effect transistors (FETs) are promising emerging devices with simple doping profiles. In these devices, the channel is uniformly doped without the need for extremely good lateral doping abruptness or high thermal budget at source/channel and drain/channel junctions. This implies that device customization requirements are simplified compared to conventional enhancement-mode FETs. However, junctionless FETs have been discussed exclusively in the context of MOSFET replacement assuming other CMOS manufacturing, circuit and interconnect paradigms to be preserved intact.

As CMOS technology advances into the nanoscale, the continuous push for low power, high performance, and dense volatile memory is reaching its limit. Moreover, in the nanometer regime complex design rules and manufacturing costs are escalating as it is getting increasingly difficult to control manufacturing process parameters. In this paper, we propose a novel 10 transistor based volatile Nanowire Random Access Memory (10T-NWRAM) which is highly scalable and manufacturing friendly since it is based on the very regular N3ASIC fabric.