Andras’s Lab
(Archival from University of Massachusetts Amherst)

Publications

2011

3-D Integration Requirements for Hybrid Nanoscale-CMOS Fabrics

Pavan Panchapakeshan, Priyamvada Vijayakumar, Pritish Narayanan, Chi On Chui, Csaba Andras Moritz

in Proceedings of IEEE International Conference on Nanotechnology (IEEE NANO) , pp. 849-853 , 2011 , PDF
Nanoscale Application Specific Integrated Circuits

Csaba Andras Moritz, Pritish Narayanan, Chi On Chui

in Nanoelectronic Circuit Design, N. K. Jha and D. Chen, Eds. Springer New York , pp. 215-275 , 2011 , Book Chapter ,
Book

2010

Programmable Cellular Architectures at the Nanoscale

Pritish Narayanan, Teng Wang, Csaba Andras Moritz

Nano Communication Networks , Vol. 1 , No. 2 , pp. 77-85 , 2010 , PDF
Parameter Variability in Nanoscale Fabrics: Bottom-Up Integrated Exploration

Pritish Narayanan, Michael Leuchtenburg, Jorge Kina, Prachi Joshi, Pavan Panchapakeshan, Chi On Chui, Csaba Andras Moritz

in Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT) , pp. 24-31 , 2010 , PDF
Incorporating Heterogeneous Redundancy in a Nanoprocessor for Improved Yield and Performance

Priyamvada Vijayakumar, Pritish Narayanan, Israel Koren, C. Mani Krishna, Csaba Andras Moritz

in Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT) , pp. 273-279 , 2010 , PDF
Towards Logic Functions as the Device

Prasad Shabadi, Alexander Khitun, Pritish Narayanan, Mingqiang Bao, Israel Koren, Kang L. Wang, Csaba Andras Moritz

in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch) , pp. 11-16 , 2010 , PDF

2009

Heterogeneous 2-level Logic and its Density and Fault Tolerance Implications in Nanoscale Fabrics

Teng Wang, Pritish Narayanan, Csaba Andras Moritz

IEEE Transactions on Nanotechnology , Vol. 8 , Article 1 , pp. 22-30 , 2009 , PDF
Impact of Process Variation on NASIC Nanoprocessors with 2-way Redundancy

Michael Leuchtenburg, Pritish Narayanan, Teng Wang, Csaba Andras Moritz

in Proceedings of IEEE International Conference on Nanotechnology (IEEE NANO) , pp. 737-739 , 2009 , PDF
Validating Cascading of Crossbar Circuits with an Integrated Device-Circuit Exploration

Pritish Narayanan, Chi On Chui, Csaba Andras Moritz

in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch) , pp. 37-42 , 2009 , PDF
Manufacturing Pathway and Associated Challenges for Nanoscale Computational Systems

Pritish Narayanan, Kyoung Won Park, Chi On Chui, Csaba Andras Moritz

in Proceedings of IEEE International Conference on Nanotechnology (IEEE NANO) , pp. 119-122 , 2009 , PDF

2008

Image Processing Architecture for Semiconductor Nanowire based Fabrics

Pritish Narayanan, Teng Wang, Michael Leuchtenburg, Csaba Andras Moritz

in Proceedings of IEEE International Conference on Nanotechnology (IEEE NANO) , pp. 677-680 , 2008 , PDF
CMOS Control Enabled Single-Type FET NASIC

Pritish Narayanan, Michael Leuchtenburg, Teng Wang, Csaba Andras Moritz

IEEE Computer Society Annual Symposium on VLSI , pp. 191-196 , 2008 , Best Paper Award , PDF, Extended PDF
Impact of Process Variation in Fault-Resilient Streaming Nanoprocessors

Michael Leuchtenburg, Pritish Narayanan, Teng Wang, Csaba Andras Moritz

International Conference on Nano-Networks , pp. 26–27 , 2008 , PDF
NASICs: A Nanoscale Fabric for Nanoscale Microprocessors

Teng Wang, Pritish Narayanan, Michael Leuchtenburg, Csaba Andras Moritz

IEEE International Nanoelectronics Conference (INEC) , pp. 989-994 , 2008 , PDF

2007

Fault-Tolerant Nanoscale Processors on Semiconductor Nanowire Grids

Csaba Andras Moritz, Teng Wang, Pritish Narayanan, Michael Leuchtenburg, Yao Guo, Catherine Dezan, Mahmoud Bennasser

IEEE Transactions on Circuits and Systems I, Special issue on Nanoelectronic Circuits and Nanoarchitectures , Vol. 54 , No. 11 , pp. 2422-2437 , 2007 , PDF
Synchronization Coherence: A Transparent Hardware Mechanism for Cache Coherence and Fine-Grained Synchronization

Yao Guo, Vladimir Vlassov, Raksit Ashok, Richard Weiss, Csaba Andras Moritz

Elsevier Journal of Parallel and Distributed Computing (JPDC) , Vol. 68 , No. 2 , pp. 165-181 , 2007 , PDF
Designing Memory Subsystems Resilient to Process Variations

Mahmoud Bennasser, Yao Guo, Csaba Andras Moritz

IEEE Computer Society Annual Symposium on VLSI , pp. 357-363 , 2007 , PDF
Combining 2-level Logic Families in Grid-based Nanoscale Fabrics

Teng Wang, Pritish Narayanan, Csaba Andras Moritz

in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch) , pp. 101-108 , 2007 , PDF

2006

Combining Circuit Level and System Level Techniques for Defect-Tolerant Nanoscale Architectures

Teng Wang, Mahmoud Bennasser, Yao Guo, Csaba Andras Moritz

in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch) , 2006 , PDF
Compiler-Based Adaptive Fetch Throttling for Energy Efficiency

Teng Wang, Yao Guo, Israel Koren, C. Mani Krishna

IEEE International Symposium on Performance Analysis of Systems and Software , pp. 112-119 , 2006 , PDF
Towards Defect-Tolerant Nanoscale Architectures

Csaba Andras Moritz, Teng Wang

in Proceedings of IEEE International Conference on Nanotechnology (IEEE NANO) , pp. 331-334 , 2006 , PDF
Self-Healing Wire-Streaming Processors on 2-D Semiconductor Nanowire Fabrics

Teng Wang, Mahmoud Bennasser, Yao Guo, Csaba Andras Moritz

Nano Science and Technology Institute (NSTI) Nanotech , pp. 312 - 315 , 2006 , PDF
Power and Failure Analysis of CAM Cells Due to Process Variations

Mahmoud Bennasser, Csaba Andras Moritz

IEEE International Conference on Electronics, Circuits and Systems (ICECS) , pp. 608 - 611 , 2006 , PDF

2005

PARE: A Power-Aware Data Prefetching Engine

Yao Guo, Mahmoud Bennasser, Csaba Andras Moritz

International Symposium on Low Power Electronics and Design , pp. 339 - 344 , 2005 , PDF
Wire-Streaming Processors on 2-D Nanowire Fabrics

Teng Wang, Mahmoud Bennasser, Yao Guo, Csaba Andras Moritz

Nano Science and Technology Institute (NSTI) Nanotech , pp. 619 - 622 , 2005 , PDF, Extended PDF

2004

Coupling Compiler-Enabled and Conventional Memory Accessing for Energy Efficiency

Raksit Ashok, Saurabh Chheda, Csaba Andras Moritz

ACM Transactions on Computer Systems (TOCS) , Vol. 22 , Article 2 , pp. 180-213 , 2004 , PDF
Opportunities and Challenges in Application-Tuned Circuits and Architectures Based on Nanodevices

Teng Wang, Zhenghua Qi, Csaba Andras Moritz

in Proceedings of the First Conference on Computing Frontiers , pp. 503 - 511 , 2004 , PDF
Energy Characterization of Hardware-Based Data Prefetching

Yao Guo, Saurabh Chheda, Israel Koren, C. Mani Krishna, Csaba Andras Moritz

IEEE International Conference on Computer Design , pp. 518-523 , 2004 , PDF
Runtime Biased Pointer Analysis and Its Application on Energy Efficiency

Yao Guo, Saurabh Chheda, Csaba Andras Moritz

Workshop on Power-Aware Computer Systems (PACS) , pp. 1-12 , 2004 , PDF
Latching on the Wire and Pipelining in Nanoscale Designs

Csaba Andras Moritz, Teng Wang

Workshop on Non-Silicon Computation , pp. 1-7 , 2004 , PDF

Pages